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Impact of FPGA Architecture on Resource Sharing in High-Level Synthesis
High Level Synthesis (HLS) Explanation 11: Introduction to Finding Pipelined Schedules
Video 3: Optimizing Power, Performance and Area with High-Level Synthesis (HLS)
Dataflow Accelerators for DNNs using High-Level Synthesis | Guest Lecture at Georgia Tech
FLOSS Tools for High Level Synthesis Integrating the FPGA into the Operating System
SRC Formally Verified High Level Synthesis
Dataflow Hardware Acceleration of DNNs with High-Level Synthesis | Guest Lecture at Yale University
Functional interfaces in higher-level synthesis
SORS/WomenInBSC: Open-Source High-Level Synthesis Research for Automated FPGA/ASIC Acceleration
High-level Data-Centric Parallel Programming for high performance BLAS on FPGAs - Xilinx XOHW20 161
HPVM: Extending LLVM For Compiling to Heterogeneous Parallel Systems
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Last Updated: August 15, 2026
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