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FReaC Cache: Folded-Logic Reconfigurable Computing in the Last Level Cache
EECS 370 Review #11 - Reverse Engineering the Cache
WANC:93 A Conflict-Aware Capacity Control Mechanism for Last-Level Cache
34C3 - ASLR on the line - deutsche Übersetzung
Detecting Spectre Attacks Using Hardware Performance Counters (0622)
Lecture 31 - Cache Performance
Every Level of Reverse Engineering Explained
ECC'17: Reverse Engineering x86 Processor Microcode
#HITB2016AMS D2T1 - Cache Side Channel Attacks: CPU Design As A Security Problem - Anders Fogh
USENIX Security '17 - Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX
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Last Updated: August 15, 2026
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